1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same. More particularly, the present invention relates to a multi-level semiconductor device in which a plurality of transistors are stacked and method of fabricating the same.
2. Description of the Related Art
Conventionally, a semiconductor device may include transistors disposed on a bulk substrate to form circuits. However, the semiconductor device having transistors disposed on a bulk substrate has a limited integration density, and the integration density is further restricted because the device requires a structure for isolating the NMOS transistor and PMOS transistors that are formed on the same level.
Recently, a multi-level semiconductor device having a plurality of transistor layers on the semiconductor substrate has been investigated in order to solve latch-up problems and enhance integration density in the CMOS structure. Such a multi-level transistor structure may be employed in a SRAM cell having a high integration density and a CMOS structure.
A CMOS SRAM cell may use a PMOS transistor as load transistor. Two load transistors connected to Vcc and two drive transistors connected to Vss may form a latch. Two transfer transistors connected to respective bit lines and a word line WL may be connected to the latch. When the CMOS SRAM cell is formed on a bulk substrate, load transistors, which may be PMOS transistor, and drive transistors, which may be NMOS transistors, may be formed so close to each other that latch-up may occur. Thus the integration density may be limited in order to isolate PMOS transistors and NMOS transistors.
An SRAM cell could also be implemented as a multi-level transistor structure. However, in a multi-level structure, a transistor on an upper semiconductor layer may be connected to a contact pattern through a small contact area where the contact pattern meets a semiconductor layer. Due to a small contact area of the contact pattern with the semiconductor layer, resistance may be high. Further, in such a structure, increasing the drain region of a load transistor or forming a thick semiconductor layer in order to decrease resistance may result in increasing the leakage current. Also, if ions are injected into a node diffusion layer in a portion contacting the contact pattern, in order to decrease the contact resistance between the contact pattern and the node diffusion layer, resistance may increase due to decrease in concentration of the drain region of the load transistor having opposite conductivity.